Register File Design in Automatically Generated ASIPs

Register File Synthesis in ASIP Design

Interest in synthesis of Application Specific Instruction Set Processors or ASIPs has increased considerably and a number of methodologies have been proposed for ASIP design. A key step in ASIP synthesis involves deciding architectural features based on application requirements and constraints. In this report we observe the effect of changing register file size on the performance as well as pow...

A proposed synthesis method for Application-Specific Instruction Set Processors

Due to the rapid technology advancement in integrated circuit era, the need for the high computation performance together with increasing complexity and manufacturing costs has raised the demand for high-performance configurable designs; therefore, the Application-Specific Instruction Set Processors (ASIPs) are widely used in SoC design. The automated generation of software tools for ASIPs is a...

Review of “C Compiler Design for a Network Processor”

This review describes the approach and results from the paper by Wagner and Leupers [1]. The methods they have developed for compilers for application specific instruction set processors (ASIPs) and specifically network processors (NPs) with bit-packet addressing are mainly concentrated to extensions to the traditional register allocation by graph coloring. ASIPs are used in areas where general...

A Power Aware Cache and Register File Design Space Exploration

A Performance Maximization Algorithm to Design ASIPs under the Constraint of Chip Area Including RAM and ROM Sizes

In designing ASIPs (Application Specific Integrated Processors) the papers investigated so far have almost focused on the optimization of the CPU core and did not pay enough attention to the optimization of the RAM and ROM size together. This paper overcomes this limitation and proposes an optimization algorithm to define the best tradeoff between the CPU core, RAM and ROM of an ASIP chip to ac...